Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, improvements in integration density have come from repeated reductions in minimum feature size, allowing more components to be integrated into a given chip area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limitation comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase.
Among the efforts for resolving the above-discussed limitations, three-dimensional integrated circuit (3DIC) and stacked dies are commonly used. Through-silicon vias (TSV) are often used in 3DIC and stacked dies for connecting dies. In this case, TSVs are often used to connect the integrated circuits on a die to the backside of the die. In addition, TSVs are also used to provide a short grounding path for grounding the integrated circuits through the backside of the die, which is typically covered by a grounded aluminum film.
FIG. 1 illustrates a cross-sectional view of an intermediate structure in the formation of a conventional TSV, wherein the intermediate structure includes silicon substrate 2, interlayer dielectric 4, and passivation layer 6. Electrode pad 8 is formed underlying passivation layer 6, and exposed through an opening in passivation layer 6. TSV 10 is formed through an opening in electrode pad 8 into interlayer dielectric 4 and silicon substrate 2.
The structure shown in FIG. 1 suffers from significant chip area penalty. Since the TSV is encircled by electrode pad 8, electrode pad 8 occupies a large chip area, and the corresponding chip area directly underlying electrode pad 8 cannot be used to form semiconductor devices. In addition, the formation of the TSV 10 involves forming and patterning a plurality of insulating films, and hence the manufacturing cost is high. New TSV structures and formation methods are thus needed.